CPU

‘Unity’ CPU

At the heart of the Unity platform is the ‘Unity’ CPU core. The CPU is validated in TSMC’s 28nm process and is configurable for multiple performance levels.

‘Unity’ CPU Feature Summary:

Operating frequency:
- Up to 2.5 GHz, based on process technology and optimization selection
Out-of-order pipeline:
- Increased instruction throughput; 256 in-flight instruction capable
Distributed instruction decoding:
- Optimizes design for power and performance through localized instruction decoding
Distributed register files:
- Reduces register rename complexity and register file ports
- General Purpose, F-Point, Address, and Branch Jump Target register files
Distributed register renaming:
- Localized to each functional unit for register files owned by the functional unit to achieve higher instruction throughput and simplify register rename logic
- Capable of up to 63 physical registers per unit
Instruction prefetch structure:
- Reduces instruction dispatch time
Branch Predictor:
- Reduces memory access times / improves execution performance
- 2048 2-bit saturating branch predictor
L0 and L1 I-caches:
- Facilitate fast instruction fetch; configurable to user requirements
L1 D-cache:
- Enables fast memory accesses; configurable to user requirements
Dynamically Configurable L2 unified code and data cache:
- Enables fast memory accesses
Memory Coherency:
- Maintains consistent data across memories/caches; capable at all memory subsystems
Privilege Levels:
- Three access levels are provided with increasing access to system resources
- Ease implementation of hypervisors and virtualization; enforce isolation between processes

‘Unity’ CPU Physical Implementation

Block Diagram

Physical Implementation

A physical implementation of the ‘Unity’ CPU core, fully synthesized in TSMC’s 28nm HPC process with standard cells and memories, is available to potential customers for evaluation and development activities. Features:

A single out-of-order core, capable of issuing up to 3 instructions per cycle into 5 units (Integer, Floating Point, Memory, Branch, and Address units), for a maximum of 48 simultaneously in flight instructions
Configured with a 32 KB, 4-way set associative L1 D-Cache and a direct mapped 8KB L0 I-Cache (L0), backed by a 4-way set associative 32KB L1 I-cache; caches are connected to a 2MB memory that can be arranged as an 8-way associative L2 cache or an 8-way associative 1MB L2 cache + a 1MB on-chip memory
Interfaces: 2 UARTs, 16 GPIOs, and a Dual-Data-Rate external bus for communication with external memory mapped blocks (e.g., memory, user system interfaces)
External bus configurable for 64-bit, 32-bit or 16-bit operation

For more information on the ‘Unity’ CPU implementation, Contact us here.